Abstract—It is well known that in Static Random Access Memory (SRAM) cells configured with single-ended bit lines, whenever a write operation is performed, a write failure may occur. In particular, it is relatively difficult to write a logical ‘1’ to a cell if the cell currently stores a logical ‘0’. It is thus necessary to provide a method of resolving write failures in memory cells. In this paper, a novel seven-transistor (7T) two-port SRAM cell incorporating an assist circuit is proposed. Wherein, the assist circuit is used to deal with the memory cell failures. During a write operation, this circuit is activated to connect a diode-connected transistor to the source of the drive transistor located near to the write bit line. Accordingly, it can provide an efficient solution to the writing ‘1’ issue to improve write operations in this manner. Simulation results for the proposed cell design confirm that there is a conspicuous improvement over the conventional two-port SRAM cells, and fast writing also can be achieved.
Index Terms—Two-port, assist circuit, single-ended, static random access memory, read-write control circuit.
Wen-Chieh Wu is with the Department of Digital Media Design, Hwa Hsia University of Technology, New Taipei City, Taiwan.
Ming-Chuen Shiau is with the Department of Electrical Engineering, Hsiuping University of Science and Technology, Taichung City, Taiwan.
Chien-Cheng Yu is with the Department of Electronic Engineering, Hsiuping University of Science and Technology. He is currently working toward the Ph.D. degree at National Chung Hsing University, Taichung City, Taiwan (corresponding author e-mail: jenkenyu@gmail.com).
Ching-Chih Tsai is with the Department of Electrical Engineering, National Chung Hsing University, Taichung City, Taiwan.
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Cite:Wen-Chieh Wu, Ming-Chuen Shiau, Chien-Cheng Yu, and Ching-Chih Tsai, "Two-Port SRAM Cell with Improved Write Operation," International Journal of Information and Electronics Engineering vol. 8, no. 3, pp. 41-45, 2018.