High-Speed Designed Area-Efficient Vlsi Architecture Of Three -Operand Binary Adder

Authors

  • Dr. Sk. M. Shabber , Sana Venkata Naga Radhika, Pakanati Paleswara Rao, R Thanneeru Balaji, Shaik Jani Basha Author

DOI:

https://doi.org/10.48047/yxvfap86

Keywords:

.

Abstract

The basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms is Three-operand binary adder. To perform the three-operand addition Carry-save adder (CS3A) is the widely used technique. However, the ripple carry stage in the CS3A results in high propagation delay of O(n). 

Downloads

Download data is not yet available.

Downloads

Published

01.05.2026

Issue

Vol. 16 No. 2 (2026): volume 16 issue 2(2026)

Section

Articles

License

You are free to:

  1. Share — copy and redistribute the material in any medium or format for any purpose, even commercially.
  2. Adapt — remix, transform, and build upon the material for any purpose, even commercially.
  3. The licensor cannot revoke these freedoms as long as you follow the license terms.

Under the following terms:

  1. Attribution — You must give appropriate credit , provide a link to the license, and indicate if changes were made . You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
  2. No additional restrictions — You may not apply legal terms or technological measures that legally restrict others from doing anything the license permits.

Notices:

You do not have to comply with the license for elements of the material in the public domain or where your use is permitted by an applicable exception or limitation .

No warranties are given. The license may not give you all of the permissions necessary for your intended use. For example, other rights such as publicity, privacy, or moral rights may limit how you use the material.

How to Cite

High-Speed Designed Area-Efficient Vlsi Architecture Of Three -Operand Binary Adder. (2026). International Journal of Information and Electronics Engineering, 16(2), 162-168. https://doi.org/10.48047/yxvfap86