Design And Dvelopment Of 64-Bit Alu Desing Using Vedic Mathematics
DOI:
https://doi.org/10.48047/w8zcfx71Keywords:
Arithmetic Logic Unit (ALU), Vedic Mathematics, UrdhvaTiryagbhyam, 64-bit ALU, VLSI Design, High-Speed Computing, Low Power Consumption, Hardware Description Language (HDL), FPGA Implementation, Parallel Processing, Digital Signal Processing (DSP), Pipelining.Abstract
The Arithmetic Logic Unit (ALU) is a fundamental component of modern processors, responsible for performing arithmetic and logical operations essential to computational systems. With the increasing demand for high-speed and low-power digital systems, efficient ALU design has become a critical area of research in VLSI technology. This paper presents the design and implementation of a 64-bit ALU using Vedic Mathematics, aimed at enhancing computational speed and reducing hardware complexity.
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