High-Speed Designed Area-Efficient Vlsi Architecture Of Three -Operand Binary Adder. International Journal of Information and Electronics Engineering, [S. l.], v. 16, n. 2, p. 162–168, 2026. DOI: 10.48047/yxvfap86. Disponível em: https://ijiee.org/index.php/ijiee/article/view/1122. Acesso em: 2 may. 2026.