Single-Port 5T SRAM Cell with Improved Write-Ability and Reduced Standby Leakage Current

Abstract

In this paper, a novel single-port five-transistor 
(5T) Static Random Access Memory (SRAM) cell and 
associated read/write assist is proposed. Amongst them, a voltage level conversion circuit is to provide a voltage of the respective connected word line to be lower than or equal to the power supply voltage VDD, as such the read/write-ability of the cell can be improved. Furthermore, a voltage control circuit is coupled to the sources corresponding to the driver transistors of 
each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. In addition, a pre-charging circuit is design to pull up the bit line BL of a selected column to the voltage VDD before the read or write operation. Finally, with the standby start-up circuit design, the memory cell can rapidly switch to the standby mode, and thereby reduce leakage current in 
standby. In particular, the paper introduce a two-phase reading mechanism to improve the reading speed, and thus to avoid unnecessary power consumption. Furthermore, by using the voltage level conversion circuit to pull the voltage of the signal WLC in a selected row cells lower than the power supply voltage VDD by a threshold voltage during a read operation, thereby to reduce the half-selected cells disturbance.