Junctionless CMOS Transistors with Independent Double Gates
Keywords:
CMOS, junctionless, independent gatesAbstract
Scaling is getting challenging with every
technology node. Implant process requirements for defining
conformal junctions in 3D device are very stringent. In addition,
defining gate over topography is limited by lithography. Our
solution to these problems is a novel junction-less FiNFET like
transistor. Unlike conventional FiNFET the gate definition in
this device is lithography independent. The fabricated NMOS
and PMOS shows good transistor characteristics: ION =52.3
uA/um, ION/IOFF ratio = 107, SS = 92mV/dec for NMOS and
ION =15.4 uA/um, ION/IOFF ratio = 105, SS = 90mV/dec for
PMOS. We also show inverter VTC characteristics fabricated
using this NMOS and PMOS.
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