System Level Approach to NoC Design Space Exploration

Authors

  • R. K. Jena, Member, IACSIT Author

Keywords:

NoC, PSO, analytical model, design space exploration.

Abstract

Network-on-Chip (NoC) has recently emerged as a 
communication solution for most of the System-on-Chip(SoC) design. Design space exploration and performance evaluation are the most essential task in NoC design. In this paper, we proposed a PSO based integrated design space exploration framework for the NoC design at system level. The results show that our framework optimizes the design matrices like system 
throughput and average packet latency for the target 
application.  

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Published

07.03.2012

How to Cite

System Level Approach to NoC Design Space Exploration. (2012). International Journal of Information and Electronics Engineering, 2(2), 151-155. https://ijiee.org/index.php/ijiee/article/view/81